When using Windows 2000 you must install Windows 2000 Service Pack 4 as well as all updates. You must also be logged on as an administrator to install Adept.

The Digilent NET1 module implements a proprietary application protocol used by our Adept Suite software to provide JTAG scan chain access and data transfer capability. It does not provide a general purpose Ethernet interface accessible from the FPGA on our programmable logic boards.

The Adept Suite and the Adept SDK provide the necessary software components to use the NET1 module to provide FPGA configuration capability and data transfer capability via Ethernet. The Adept SDK is required to write custom software applications on the PC to take advantage of this capability. Please visit this page to download the Adept Suite and Adept SDK.

When installing a new version of Adept, you need to uninstall the old version first. Please completely uninstall the software and then install the new version again. This should fix the problem.
If you continue to experience problems with the software you should go through the following procedure:

1. Make sure all versions of Adept are uninstalled from your computer.
2. Go to the C:WINDOWSsystem32 directory on your computer.
3. Delete jtsc.dll and dpcutil.dll from that directory.
4. Reinstall Adept

Digilent's JTAG-USB and JTAG-USB-FS cables are exclusively supported by the Digilent Adept Software. You can find a list of supported devices under the FAQ entry for "What Xilinx devices can be programmed using the Adept software?"

Adept does not currently work under Linux. However, we are working on a new version that will.

The configuration state machine inside the FPGA needs a "startup clock" to clock the final startup sequence after configuration. The startup clock source is controlled by an option setting in the "Generate Program File" process in the Xilinx ISE Project Navigator tool. The clock source should be set to JTAG-CLK to create a .bit file to be used for configuring the FPGA using a JTAG interface. The clock source should be set to CCLK for .bit files that are intended to be programmed into a Platform Flash.

When building the project make sure that the startup clock is set appropriately. You can do this in Project Navigator by right clicking on the "Generate Program File" process. Select Properties and then click Startup Options. Set the startup clock to JTAG-CLK or CCLK as appropriate.

The Xilinx iMPACT tool is capable of automatically setting the statup clock bit to JTAG-CLK if necessary during the programming process. Adept isn't capable of changing the clock source "on the fly" and the programming file must be built with the correct setting.

The current version of Adept supports the following devices:

FPGA Families

• Spartan 2E - XC2SE
• Spartan 3 - XC3S
• Spartan 3E - XC3SE (100K through 1600K gate)
• Spartan 3A - XC3SA (50K through 1400K gate)
• Spartan 3AN - XC3SAN (50K through 1400K gate)
• Virtex 2 - XC2V (untested)
• Virtex 2 Pro - XC2VP (tested for XC2VP30, untested for others)

CPLD Families

• CoolRunner 2 - XC2CA
• CoolRunner 2 - XC2C

PROM Families

• Platform Flash PROM - XCFS (not XCFP series)

Please see the Adept Suite SVF Configuration File Creation document for information on using SVF files to program other devices.

It is installed with the Digilent Adept Software. It can also be downloaded directly from the Adept software page.

If the board does not appear to be working and the FPGA or voltage regulators are getting extremely hot it is likely that the FPGA has been destroyed. An IC becoming too hot to touch is an indication of excessive current flow through the device, indicating that the FPGA or some other chip is shorted internally.

Your board is probably damaged beyond repair.

There are three likely causes of this kind of damage to the board:

The first is electrostatic discharge (ESD) damage to the I/O buffers on the FPGA. All electronic devices built using MOSFET transistors are susceptible to ESD damage. The gate insulation layer on a MOSFET transistor is extremely thin and the high voltage associated with static charge can easily produce an arc across the gate, destroying the transistor. Xilinx devices have some internal ESD protection and Digilent places external ESD protection diodes on many of the I/O pins, but these can't always provide absolute protection. ESD safe-handling procedures should always be used when handling boards with MOSFET devices.

A second possible cause of damage to our boards is logic-level conflicts between pins on the FPGA or pins on other devices on the board or on peripheral devices. If two output pins are inadvertently connected and attempt to drive opposing logic levels (i.e., one output driving a logic high connected to another output driving a logic low), excessive current will flow. By default, the output buffers on most Xilinx FPGA and CPLD devices can drive 24mA of current. This level of current drive is necessary to produce very short rise and fall times on output signals. However, output buffers are not able to sustain this current flow continuously and will overheat and be destroyed. A common failure when this occurs is a short between VCC and ground through the destroyed output buffer. Because the I/O assignments on FPGA and CPLD devices are flexible, it is extremely important to avoid this problem by not making conflicting assignments of output pins and ensuring that the logic design doesn't allow output drive conflicts to occur. To help reduce the likelihood of this kind of problem, Digilent places current limiting resistors in series with many of the I/O signals on our boards, but this is not always possible, particularly for signals that are intended to allow operation at very high speeds.

The third possible cause of damage is the inadvertent creation of short circuits between I/O pins while probing the board with test equipment. If an oscilloscope, logic analyzer, or multimeter probe accidentally touches two I/O signals that happen to be driving opposite logic levels, this will produce the same situation as described above. This short circuit will cause excessive current to flow through the output buffers, possibly destroying one or both of them.

With all Digilent system boards users must be very careful not to create situations leading to the above described problems. In general, if this happens, the board is not repairable. We can not accept returns on boards that are out of warranty.

If the board does not appear to be working and the FPGA or voltage regulators are getting extremely hot it is likely that the FPGA has been destroyed. An IC becoming too hot to touch is an indication of excessive current flow through the device, indicating that the FPGA or some other chip is shorted internally.

Your board is probably damaged beyond repair.

There are three likely causes of this kind of damage to the board:

The first is electrostatic discharge (ESD) damage to the I/O buffers on the FPGA. All electronic devices built using MOSFET transistors are susceptible to ESD damage. The gate insulation layer on a MOSFET transistor is extremely thin and the high voltage associated with static charge can easily produce an arc across the gate, destroying the transistor. Xilinx devices have some internal ESD protection and Digilent places external ESD protection diodes on many of the I/O pins, but these can't always provide absolute protection. ESD safe-handling procedures should always be used when handling boards with MOSFET devices.

A second possible cause of damage to our boards is logic-level conflicts between pins on the FPGA or pins on other devices on the board or on peripheral devices. If two output pins are inadvertently connected and attempt to drive opposing logic levels (i.e., one output driving a logic high connected to another output driving a logic low), excessive current will flow. By default, the output buffers on most Xilinx FPGA and CPLD devices can drive 24mA of current. This level of current drive is necessary to produce very short rise and fall times on output signals. However, output buffers are not able to sustain this current flow continuously and will overheat and be destroyed. A common failure when this occurs is a short between VCC and ground through the destroyed output buffer. Because the I/O assignments on FPGA and CPLD devices are flexible, it is extremely important to avoid this problem by not making conflicting assignments of output pins and ensuring that the logic design doesn't allow output drive conflicts to occur. To help reduce the likelihood of this kind of problem, Digilent places current limiting resistors in series with many of the I/O signals on our boards, but this is not always possible, particularly for signals that are intended to allow operation at very high speeds.

The third possible cause of damage is the inadvertent creation of short circuits between I/O pins while probing the board with test equipment. If an oscilloscope, logic analyzer, or multimeter probe accidentally touches two I/O signals that happen to be driving opposite logic levels, this will produce the same situation as described above. This short circuit will cause excessive current to flow through the output buffers, possibly destroying one or both of them.

With all Digilent system boards users must be very careful not to create situations leading to the above described problems. In general, if this happens, the board is not repairable. We can not accept returns on boards that are out of warranty.

You can download reference manuals, schematics, and reference designs by clicking the More Info button for the relevant product in our online catalog. Also, you can click the "support" tab and select your product in the "product name" field.

If there is a problem with the switch working intermittently then it is most likely due to dirty contacts. First, try cleaning the switch with either electrical component cleaner or isopropyl alcohol and a q-tip. The next possibility is a programming error. To verify, your board should be reprogrammed with a BIST or other demo project that can verify the switches’ functionality.

When we designed the 40-pin interface between system boards and accessory boards we decided to number pins the same way on both system boards and accessory boards. If the board is positioned so that the connector is facing up, pin 1 is the left-most, inner pin toward the center of the board. Pin 2 is the left-most, outer pin toward the edge of the board, and so on. The odd-numbered pins are on the inner row and the even-numbered pins are on the outer row. This pin numbering is the same on both system boards and accessory boards.

To connect an accessory board to a system board, the accessory board must be rotated relative to the system board to mate the connectors. The odd- numbered pins on the accessory board will mate with the odd-numbered pins on the system board, and similarly for the even-numbered pins. However, pin 1 on the accessory board doesn't mate with pin 1 on the system board, it mates with pin 39. Pin 2 on the accessory board mates with pin 40 on the system board, and so on.

An easy way to remember the pin mating is as follows: the system board pin number and accessory board pin number must add up to 40 for odd-numbered pins and 42 for even-numbered pins. For example, pin 3 mates with pin 37 (3 + 37 = 40) and pin 4 mates with pin 38 (4 + 38 = 42).

We recommend that you use a Test Point Header (TPH), a Module Interface Board (MIB) or a Digilent Breadboard 1 (DBB1). These boards all provide male header pins that are tied to the FPGA signals from the system board. These header pins are 25-mil square pins spaced at 100 mils and allow for easy connection using standard logic analyzer or oscilloscope probes.

Care must be taken when probing FPGA pins as creating a short circuit can damage the FPGA on the system board. See the above entry under "Basic Troubleshooting" for a more complete description.

Digilent system boards use the Hirose FX2-100P-1.27DS connector. Refer to the Hirose FX2 connector family data sheet to find the mating part that meets your requirements. One source of low volume quantities of Hirose FX2 connectors is Digi-Key.

Xilinx FPGAs divide the I/O pins into banks. Each bank is allowed to have a different operating voltage. In general, Digilent FPGA-based system boards operate all of the I/O banks at 3.3v. A small number of Digilent FPGA-based system boards allow one or two of the I/O banks to be set via jumpers to operate at a different voltage. Refer to the reference manual for a specific board to determine what I/O voltages are supported.

When an I/O bank is operated at 3.3V, the only I/O standards supported by Xilinx FPGAs are LVTTL and LVCMOS 3.3V.

For probing FPGA I/O signals, we recommend using either the FX2 Breadboard (FX2BB) or the FX2 Wire Wrap (FX2WW) board with our 6-pin gender changers. All I/O signals from the Hirose connector on the system board pass through the FX2BB and are accessible via the 100-mil-spaced 25-mil pin connectors on the FX2BB using standard logic analyzer probes.

Care must be taken when probing FPGA pins as creating a short circuit can damage the FPGA on the system board. See the FAQ entry under "Basic Troubleshooting" for a more complete description.

The short answer is "No". None of the Xilinx FPGA families used on current Digilent FPGA-based programmable logic system boards have 5V-tolerant inputs.

There are some Xilinx FPGA families, like the Spartan 2E, that can tolerate 5V inputs for short times. A careful reading of the electrical ratings section of the appropriate data sheet (including all of the notes) will generally provide a definitive answer.

The primary problem with regard to 5V tolerance of the inputs on Xilinx FPGAs is caused by excessive current flow through the protection diodes on the input buffer. Digilent places current-limiting resistors in series between the FPGA I/O pin and connector pin on some I/O signals on some boards. On I/O signals with the current-limiting resistors in place, 5V inputs are allowed. It is preferable, however, not to bring 5V inputs onto a board if at all possible.

In general, boards that have Pmod connectors, like the Basys and Nexys families, will have current-limiting resistors in place on all I/O signals going to the Pmod connectors. Some boards with the 2x20 accessory connectors have current-limiting resistors in place and some do not. Refer to the board schematic to determine if a current-limiting resistor is in place for any specific I/O signal.

This information is generally provided in a pin-out table in the board's reference manual. This information can also be obtained from the board's schematic. Board reference manuals and schematics can be downloaded from our web site. The links can be found on the Documentation page or on a particular board's catalog page in the Products section of our web site. Some system boards have master user contraint files (UCF) that provide the pin specificationd for ISE projects.

The reference manual and the support CD for the board were created by Xilinx and describe the kit that Xilinx ships. We are not licensed to distribute Xilinx software. Support inquiries for boards purchased from Xilinx should be directed to Xilinx. We can provide some support for hardware-related problems on boards purchased from Xilinx but we can not provide support for the ancillary material (such as reference projects) provided by Xilinx.

There is nothing wrong with your board. This is a known issue with the Spartan 2E family of FPGAs. The Spartan 2E chip family was originally developed as the Virtex-E family. When Xilinx changed the family designation from Virtex-E to Spartan 2E, they forgot to change the Family ID field in the Device ID code built into the chip. Therefore, the Spartan 2E family chips are identified as Virtex-E. It will have no adverse effect on the project. The project will load and run properly if there are no errors in it.

Digilent currently uses VHDL for all programmable logic reference design development. We do not have any logic design examples in other languages.

XUPV2P must not be used for new installations of ISE WebPACK. To use this board, you must already be a current Xilinx development tools license holder (version 10.1 or earlier).

Currently, the only version of the Xilinx software available for download from the Xilinx website that still supports the XUPV2P is ISE webPACK 10.1.

The Basys and Nexys2 boards contain the Digilent USB circuit, not the Xilinx USB circuit. See the "USB Issues" and "Adept Software" sections above for a more complete discussion.

You need to use the free Adept Software available for download from our web site to program your board using the USB interface. Download and install the Digilent Adept software and then refer to the included user's manual for instructions on configuring your board.

All programming files are generated using Xilinx ISE or other software packages you may be using. Configuring the FPGA with the programming file is accomplished with Adept.

Another option for users who have a PC with a parallel port is to use our JTAG3 programming cable. There is a 6-pin JTAG header on some Digilent system boards that allows use of the JTAG3 cable. The Digilent JTAG3 programming cable is supported by XIlinx iMPACT.

ModelSim is produced and licensed by Mentor Graphics. ModelSim XE is a version of ModelSim licensed and distributed by Xilinx in earlier version of the Xilinx ISE Foundation and Xilinx ISE WebPACK software products. Because ModelSim XE is Xilinx proprietary software, it must be licensed through Xilinx. They provide an on-line licensing system here.

All Digilent Atmel AVR microcontroller-based embedded control boards require an appropriate power supply, a programming cable, software development tools, and in-system programming software. The power supply and programming cable are not included with the board and must be purchased in addition to the board.

The type of power supply to use depends on the intended application. Digilent has available wall-wart type power supplies and battery packs that are suitable for use with our embedded control boards. The reference manual for each board specifies the safe input voltage range to be used with the voltage regulator on the board.

There are many options for software development tools to use with Atmel AVR microcontrollers.

For assembly language development, Digilent recommends Atmel AVR Studio. This is a free software toolset that can be downloaded from the Atmel web site. It includes an integrated development environment, assembler, debugger that supports debugging via simulation and the Atmel JTAG ICE-MKII, and in-system programming support using the Atmel AVR-ISP In-System Programmer.

For C programming language development, Digilent recommends the WinAVR toolset. WinAVR is based on the GCC compiler tool chain and is free for download here. The WinAVR toolset provides a GCC-based compiler, debugger, and in-system programming software. The latest version of Atmel AVR Studio also includes support for WinAVR-based C projects.

Programming a completed design into the microcontroller on the board requires both in-system programming hardware and software. All Digilent AVR-based embedded control boards are designed to work with Digilent JTAG-USB or JTAG USB-FS cables. Some boards, like the Cerebot, also support the Atmel AVR-ISP In-System Programmer as well as the JTAG ICE-MKII. This is a hardware device that provides in-system debugging as well as in system programming capability.

Digilent provides free in-system programming software, the Digilent AVR Programmer, for use with our programming cables. This tool can be downloaded from the Digilent web site. The Atmel AVR Studio application provides in-system programming support using the Atmel AVR-ISP or JTAG ICE-MKII. The WinAVR toolset provides in-system programming software that supports the Atmel AVR-ISP.

There are various other third-party development and programming toolsets available, but Digilent is unable to provide recommendations or support for them.

Digilent programmable logic boards ship with an appropriate power supply and programming cable, as needed. All Digilent programmable logic boards feature programmable logic devices from Xilinx. Appropriate software is needed to develop logic designs to be loaded onto the boards. Digilent does not produce the logic design and synthesis software. Xilinx has three options for design and synthesis software.

Xilinx ISE is a complete, full-featured, logic design environment. It supports both schematic entry and HDL entry of designs and supports both the VHDL and Verilog hardware definition languages. ISE must be licensed from Xilinx, although the Xilinx University Program (XUP) provides free licenses for most academic users.

The Xilinx ISE WebPACK™ is a subset of the full ISE tool that anyone can download for free from the Xilinx web site. It requires a free license that can be obtained via registration on the Xilinx web site. WebPACK provides basic design entry, synthesis, and simulation support for the smaller devices in most chip families. It does not provide advanced floor-planning and optimization tools.

In addition to the ISE-based logic design tool sets, Xilinx provides the Embedded Development Kit (EDK). EDK is used to develop processor-based designs using either the MicroBlaze soft processor core, or the PowerPC hard processor cores available on some of the Virtex FPGA families. EDK must be licensed from Xilinx and there is no free subset currently available.

There are also various third-party design entry and synthesis tools available, but Digilent is unable to provide recommendations or support for them.

In addition to design entry and synthesis tools, software is needed to download the design into the board. There are two primary options for this. Most Digilent programmable logic boards can be programmed using the Xilinx iMPACT tool, which is part of the ISE and WebPACK software products. Some Digilent boards, such as the Basys2, require the Digilent Adept software to download designs onto the board.

The Xilinx iMPACT tool is compatible with any Xilinx programming cables, the Xilinx USB interface, and the JTAG-3 cable. The Digilent Adept software is compatible with the Digilent USB interface. Xilinx and Digilent both have USB interfaces, but they are incompatible. Some Digilent boards, like the Basys2 and Nexys2, provide the Digilent USB interface. Other Digilent boards, like the XUP-V2Pro and the Spartan 3E Starter Board, provide the Xilinx USB interface (licensed from Xilinx). The appropriate programming software to use depends on the specific USB interface on the board.

Most Digilent programmable logic boards provide a 6-pin JTAG header. Any Digilent programming cable, either parallel port or USB-based, can be used to program the board via this header, even if the board also contains an on-board programming circuit. Using this header and a JTAG-3 cable, any board can be programmed using the Xilinx iMPACT tool.

XUP-V2Pro & XUPV5 boards: These boards ship with the necessary power supply and programming cables, and are primarily intended for use with the Xilinx EDK, although the ISE tools can be used to develop logic-only designs. However, the feature sets of these boards are sufficiently large and complex that taking full advantage of their capabilities requires the use of Xilinx EDK.

Make sure you are using the latest version of the appropriate Xilinx design software. Uninstall the old version first, then install the newest version. Also make sure that you have installed the latest service pack for the design software you are using. We are able to answer board-specific software questions, but general software support questions should be directed to Xilinx.

If you still have questions, contact us at support@digilentinc.com. Please be sure to identify the software package that you're using, the service pack, your operating system version, as well as a thorough description of the problem and any relevant screenshots or error messages.

BSDL is an acronym for Boundary Scan Description Language. Each Xilinx device contains an idcode that identifies what it is. This idcode contains fields for manufacturer, device family, and device type. iMPACT compares the idcode read from the device with the idcode specified in the BSDL file to make sure that they match. The error indicates that the two don't match. A common reason for this error is that the wrong device was specified when the project was created.

The DIO1/DIO2 will work with these newer boards but with limited functionality. These two I/O boards where designed to work with the D2/D2E boards.

The DIO4/DIO5 will work with these older boards but with limited functionality. These two I/O boards were designed to work with the D2SB/D2FT, Pegasus, and Spartan-3 boards.

You can reconfigure those CPLDs but we don't recommend that you do so. The factory configuration for those CPLDs is designed to use all the pins on those devices and it is highly unlikely that you can develop a design capable of driving all of the devices on the I/O board you are using. You may be able to develop an LCD driver that could work but other devices on the I/O board would no longer work. In order to reconfigure the board with the factory configuration you will have to manipulate the synthesizer in ISE because the default settings for the synthesizer will not allow you to reconfigure the CPLD.

The Xilinx XC17S200A-PD8C.

The D2SB and D2FT-300 use the Xilinx XC18V02-PC44. The D2FT-400 uses the XC18V04-PC44.

The Digilent NET1 module implements a proprietary application protocol used by our Adept 1.10 software to provide JTAG scan chain access and data transfer capability. It does not provide a general purpose Ethernet interface accessible from the FPGA on our programmable logic boards.

Adept 1.10 and the Adept SDK provide the necessary software components to use the NET1 module to provide FPGA configuration capability and data transfer capability via Ethernet. The Adept SDK is required to write custom software applications on the PC to take advantage of this capability.

You should be able find all the information you need concerning the RSK motors & encoders from the manufacturer's data sheets.

http://www.shayye.com.tw

No USB-to-parallel converter or emulator will work, but parallel port PCI add-in cards should work. The Digilent JTAG-USB cable will work with all Digilent system boards.

Digilent boards may have one of two different USB circuits. Some boards have the Digilent USB circuit and some boards have the Xilinx USB circuit. The two are not compatible. The easiest way to determine which USB circuit is on your board is to go to www.digilentinc.com and see the programming information listed for your board.

If it says "programming via the on-board USB circuit (or port)" then it has the Xilinx USB circuit and iMPACT is used to program the board.

If it says "JTAG programming via the on-board USB circuit (using the free Adept Suite Software)" then it has the Digilent USB circuit. Boards with the Digilent USB circuit are not recognized in iMPACT and require the Adept Suite software available here. This is a free download that includes the reference manual and all drivers.

The Digilent USB circuit is not intended to be a USB firmware development platform. It is intended to be a communication system for providing JTAG scan chain access and data transfer capability for our boards. Reprogramming the firmware on the board or otherwise modifying it will void the board's warranty and we cannot provide any support for users who do this.

If you wish to license the use of the Digilent USB circuit design or firmware to include in your own product, please contact us at support@digilentinc.com for more information.

The Digilent USB circuit provides a mechanism for transferring data between a PC and the system board. This is accomplished through an EPP-style register-based transfer system. This data transfer capability is not provided by the Xilinx USB circuit. The Adept Software and the Adept SDK provide the necessary software to perform data transfer operations. Most current Digilent programmable logic boards, like the Basys2 and the Nexys2, have the Digilent USB circuit built in. The Digilent JTAG-USB cable provides programming capability only: No register-based data transfer is supported by this product.

Digilent boards may have one of two different USB circuits. Some boards have the Digilent USB circuit and some boards have the Xilinx USB circuit. The two are not compatible. The easiest way to determine which USB circuit is on your board is to go to www.digilentinc.com and see the programming information listed for your board.